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lt1910 1 1910fa typical application description protected high side mosfet driver the lt ? 1910 is a high side gate driver that allows the use of low cost n-channel power mosfets for high side switching applications. it contains a completely self-contained charge pump to fully enhance an n-channel mosfet switch with no external components. when the internal drain comparator senses that the switch current has exceeded the preset level, the switch is turned off and a fault ? ag is asserted. the switch remains off for a period of time set by an external timing capacitor and then automatically attempts to restart. if the fault still exists, this cycle repeats until the fault is removed, thus protecting the mosfet. the fault ? ag becomes inactive once the switch restarts successfully. the lt1910 has been speci? cally designed for harsh operating environments such as industrial, avionics and automotive applications where poor supply regulation and/ or transients may be present. the device will not sustain damage from supply transients of C15v to 60v. the lt1910 is available in the so-8 package. fault protected high side switch l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. features applications n 8v to 48v power supply range n protected from C15v to 60v supply transients n short-circuit protected n automatic restart timer n open-collector fault flag n fully enhances n-channel mosfet switches n programmable current limit, delay time and autorestart period n voltage limited gate drive n defaults to off state with open input n available in so-8 package n industrial control n avionics systems n automotive switches n stepper motor and dc motor control n electronic circuit breaker switch drop vs load current fault in timer v + sense gate lt1910 5.1k 24v 5v fault output off on gnd irfz34 1910 ta01 10f 50v 0.1f 0.01 load + load current (a) 0 total drop (v) 0.30 0.40 0.50 4 1910 ta02 0.20 0.10 0.25 0.35 0.45 0.15 0.05 0 1 2 3 5
lt1910 2 1910fa supply voltage (pin 8) ............................... C15v to 60v input voltage (pin 4) ..................... (gnd C 0.3v) to 15v gate voltage (pin 5) ................................................ 75v sense voltage (pin 6) ........................................ v + 5v fault voltage (pin 3) .............................................. 36v current (pins 1, 2, 4, 5, 6, 8) ................................ 40ma operating temperature range (note 2) lt1910e ............................................... C40c to 85c lt1910i .............................................. C40c to 125c junction temperature range ................ C40c to 125c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) .................. 300c (note 1) 1 2 3 4 8 7 6 5 top view v + nc sense gate gnd timer fault in s8 package 8-lead plastic so t jmax = 125c, ja = 150c/w order information lead free finish tape and reel part marking package description temperature range lt1910es8#pbf lt1910es8#trpbf 1910e 8-lead plastic so C40c to 85c lt1910is8#pbf lt1910is8#trpbf 1910i 8-lead plastic so C40c to 125c lead based finish tape and reel part marking package description temperature range lt1910es8 lt1910es8#tr 1910e 8-lead plastic so C40c to 85c lt1910is8 lt1910is8#tr 1910i 8-lead plastic so C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ pin configuration absolute maximum ratings electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 12v to 48v unless otherwise noted. symbol parameter conditions min typ max units i s supply current (off state) v + = 48v, v in = 0.8v 1.2 1.9 2.5 ma i s(on) delta supply current (on state) v in = 2v, measure increase in i s 0.8 1.2 ma v inh input high voltage e-grade i-grade l l 2 3.5 v v v inl input low voltage e-grade i-grade l l 0.8 0.7 v v i in input current v in = 2v v in = 5v l l 15 55 30 110 50 185 a a c in input capacitance (note 3) 5pf v t(th) timer threshold voltage v in = 2v, adjust v t l 2.6 2.9 3.2 v v t(cl) timer clamp voltage v in = 0.8v 3.2 3.5 3.8 v i t timer charge current v in = v t = 2v 9 14 20 a v sense drain-sense threshold voltage temperature coef? cient (note 3) 50 65 0.33 80 mv %/c
lt1910 3 1910fa electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt1910e is guaranteed to meet performance speci? cations from 0c to 70c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 12v to 48v unless otherwise noted. symbol parameter conditions min typ max units i sense drain sense input current v + = 48v, v sense = 65mv 0.5 1.5 a v gate C v + gate voltage above supply v + = 8v v + = 12v l 4 7 4.5 8.5 6 10 v v v + = 24v e-grade i-grade l l 10 10 12 12 14 15 v v v + = 48v e-grade i-grade l l 10 10 12 12 14 15 v v v f(th) fault output high threshold voltage fault output low threshold voltage v in = 2v, i f = 1ma, adjust v t 3.1 3.0 3.4 3.3 3.7 3.6 v v v fol fault output low voltage i f = 1ma l 0.07 0.4 v t on turn-on time v + = 24v, v gate = 32v, c gate = 1nf 100 220 400 s t off turn-off time v + = 24v, v gate = 2v, c gate = 1nf 25 100 s t off(cl) current limit turn-off time v + = 24v, (v + C v sense ) 0.1v, c gate = 1nf 20 50 s with statistical process controls. the lt1910i is guaranteed to meet performance speci? cations over the full C40c to 125c operating temperature range. note 3: guaranteed but not tested. typical performance characteristics supply current vs supply voltage supply current vs temperature input voltage vs temperature supply voltage (v) 0 supply current (ma) 2.4 2.8 3.2 3.6 40 1910 g01 2.0 1.6 2.2 2.6 3.0 3.4 1.8 1.4 1.2 10 20 30 50 on state off state t a = 25c temperature (c) C50 0 supply current (ma) 1.0 2.0 3.0 2.5 C25 0 25 50 1910 g02 75 4.0 5.0 0.5 1.5 3.5 4.5 125 100 v + = 48v on state off state temperature (c) C50 input voltage (v) 1.0 1.2 1.4 1.6 2.0 C25 02550 1910 g03 75 125 100 1.8 0.8 v inh v inl
lt1910 4 1910fa typical performance characteristics timer charge current vs tempeature drain sense threshold voltage vs temperature mosfet gate voltage above v + (v gate C v + ) vs supply voltage mosfet gate drive current vs v gate C v + fault threshold voltage vs temperature fault output low voltage vs temperature input current vs temperature timer threshold voltage vs temperature timer clamp voltage vs temperature temperature (c) C50 0 input current (a) 40 80 120 C25 0 25 50 1910 g04 75 160 200 20 60 100 140 180 125 100 v in = 5v v in = 2v temperature (c) C50 timer threshold voltage (v) 2.7 2.8 2.9 3.0 3.2 C25 02550 1910 g05 75 125 100 3.1 2.6 v in = 2v temperature (c) C50 timer clamp voltage (v) 3.3 3.4 3.5 3.6 3.8 C25 0 25 50 1910 g06 75 125 100 3.7 3.2 v in 0.8v temperature (c) C50 timer charge current (a) 10 12 14 16 20 C25 02550 1910 g07 75 125 100 18 8 v in = v t = 2v temperature (c) C50 40 drain sense threshold voltage (mv) 50 60 70 65 C25 0 25 50 1910 g08 75 80 90 45 55 75 85 125 100 v + = 24v supply voltage (v) 0 mosfet gate voltage above v + (v gate C v + ) (v) 16 14 12 10 8 6 4 2 0 40 ltc1266 ? f04 10 20 30 50 35 51525 45 t a = 125c t a = C40c t a = 25c v gate C v + (v) 024 mosfet gate drive current (a) 1 10 100 6 8 10 12 14 16 1910 g10 0.1 v + = 8v v + = 12v v + 24v t a = 25c temperature ( o c) ?50 0 fault output low voltage (v) 0.04 0.08 0.12 0.10 ?25 0 25 50 1910 g012 75 0.16 0.20 0.02 0.06 0.14 0.18 125 100 i f = 1ma temperature (c) C50 fault threshold voltage (v) 3.2 3.3 3.4 3.5 3.7 C25 02550 1910 g11 75 125 100 3.6 3.0 3.1 v in = 2v i f = 1ma fault high threshold fault low threshold
lt1910 5 1910fa typical performance characteristics turn-on time vs temperature turn-off time vs temperature automatic restart period vs temperature temperature ( o c) ?50 turn-on time ( m s) 150 200 250 300 400 ?25 02550 1910 g13 75 125 100 350 100 v + = 24v v gate = 32v c gate = 1nf temperature ( o c) ?50 0 turn-off time ( m s) 20 40 60 50 ?25 0 25 50 1910 g014 75 80 100 10 30 70 90 125 100 v + = 24v v gate = 2v c gate = 1nf normal current limit temperature (c) C30 10 100 1000 C10 10 30 50 90 70 1910 g15 automatic restart period (ms) C50 130 110 v + = 24v c t = 3.3f c t = 0.33f c t = 0.1f c t = 1f pin functions gnd (pin 1): common ground. timer (pin 2): a timing capacitor, c t , from the timer pin to ground sets the restart time following overcurrent detection. upon detection of an overcurrent condition, c t is rapidly discharged to less than 1v and then recharged by a 14a nominal current source back to the 2.9v timer threshold, whereupon the restart is attempted. when- ever timer pulls below 2.9v, the gate pin pulls low to turn off the external switch. this cycle repeats until the overcurrent condition goes away and the switch restarts successfully. during normal operation the pin clamps at 3.5v nominal. fault (pin 3): the fault pin monitors the timer pin voltage and indicates the overcurrent condition. whenever the timer pin is pulled below 3.3v at the onset of a cur- rent limit condition, the fault pin pulls active low. the fault pin resets high immediately when the timer pin ramps above 3.4v during autorestart. the fault pin is an open-collector output, thus requiring an external pull-up resistor and is intended for logic interface. the resistor should be selected with a typical 1ma pull-up at low status and less than 2ma under worst-case conditions. in (pin 4): the in pin threshold is ttl/cmos compatible and has approximately 200mv of hysteresis. when the in pin is pulled active high above 2v, an internal charge pump is activated to pull up the gate pin. the in pin can be pulled as high as 15v regardless of whether the sup- ply is on or off. if the in pin is left open, an internal 75k pull-down resistor pulls the pin below 0.8v to ensure that the gate pin is inactive low. gate (pin 5): the gate pin drives the power mosfet gate. when the in pin is greater than 2v, the gate pin is pumped approximately 12v above the supply. it has rela- tively high impedance (the equivalence of a few hundred k) when pumped above the rail. care should be taken to minimize any loading by parasitic resistance to ground or supply. the gate pin pulls low when the timer pin falls below 2.9v. sense (pin 6): the sense pin connects to the input of a supply-referenced comparator with a 65mv nominal offset. when the sense pin is taken more than 65mv below supply, the mosfet gate is driven low and the timing capacitor is discharged. the sense pin threshold has a 0.33%/c temperature coef? cient (tc), which closely matches the tc of the drain-sense resistor formed from the copper trace of the pcb. for loads requiring high inrush current, an rc timing delay can be added between the drain-sense resistor and the sense pin to ensure that the current-sense comparator does not false trigger during start-up (see applications
lt1910 6 1910fa pin functions block diagram information). a maximum of 10k can be inserted between a drain-sense resistor and the sense pin. if current sensing is not required, the sense pin is tied to supply. v + (pin 8): in addition to providing the operating cur- rent for the lt1910, the v + pin also serves as the kelvin connection for the current-sense comparator. the v + pin must be connected to the positive side of the drain-sense resistor for proper current-sensing operation. C + + C C + 3.3v timer in 14a v + 2.9v 1.4v 75k 75k fault C + 1.4v 250 1910 bd gate sense v + 65mv C + oscillator and charge pump C + operation (refer to the block diagram) the lt1910 gate pin has two states, off and on. in the off state it is held low, while in the on state it is pumped to 12v above the supply by a self-contained 750khz charge pump. the off state is activated when either the in pin is below 0.8v or the timer pin is below 2.9v. conversely, for the on state to be activated, the in pin must be above 2v and the timer pin must be above 2.9v. the in pin has approximately 200mv of hysteresis. if it is left open, the in pin is held low by a 75k resistor. under normal conditions, the timer pin is held a diode drop above 2.9v by a 14a pull-up current source. thus the timer pin automatically reverts the gate pin to the on state if the in pin is above 2v. the sense pin normally connects to the drain of the power mosfet, which returns through a low value drain-sense resistor to supply. in order for the sense comparator to accurately sense the mosfet drain current, the v + pin must be connected directly to the positive side of the drain-sense resistor. when the gate pin is on and the mosfet drain current exceeds the level required to gener- ate a 65mv drop across the drain-sense resistor, the sense comparator activates a pull-down npn which rapidly pulls the timer pin below 2.9v. this in turn causes the timer comparator to override the in pin and set the gate pin to the off state, thus protecting the power mosfet. when the timer pin is pulled below 3.3v, the fault comparator
lt1910 7 1910fa operation also activates the open-collector npn to pull the fault pin low, indicating an overcurrent condition. when the mosfet gate voltage is discharged to less than 1.4v, the timer pin is released. the 14a current source then slowly charges the timing capacitor back to 2.9v where the charge pump again starts to drive the gate pin high. if a fault condition still exists, the sense comparator threshold will again be exceeded and the timer cycle will repeat until the fault is removed. the fault pin becomes inactive high if the timer pin charges up successfully above 3.4v (see figure 1). 3.4v 1910 f01 0v gate timer fault in overcurrent normal normal off 0v 0v 0v 5v 3.5v 2.9v v + 12v figure 1. timing diagram applications information input/supply sequencing there are no input/supply sequencing requirements for the lt1910. the in pin may be taken up to 15v with the supply at 0v. when the supply is turned on with the in pin set high, the mosfet turn-on will be inhibited until the timing capacitor charges up to 2.9v (i.e., for one restart cycle). isolating the inputs operation in harsh environments may require isolation to prevent ground transients from damaging control logic. the lt1910 easily interfaces to low cost optoisolators. the network shown in figure 2 ensures that the input will be pulled above 2v, but not exceed the absolute maximum rating for supply voltages of 12v to 48v over the entire temperature range. the optoisolator must have less than 20a of dark current (leakage) at hot in order to maintain the off state (see figure 2). drain-sense con? guration the lt1910 uses supply referenced current sensing. one input of the current-sense comparator is connected to a drain-sense pin, while the second input is offset 65mv below the supply inside the device. for this reason, pin 8 of the lt1910 must be treated not only as a supply pin, but also as the reference input for the current-sense comparator. figure 3 shows the proper drain-sense con? guration for the lt1910. note that the sense pin goes to the drain end of the sense resistor, while the v + pin is connected in 51k 100k 2k logic input 12v to 48v lt1910 gnd power ground logic ground 1 1910 f02 4 fault in timer v + sense gate 3 4 2 8 6 5 lt1910 r1 5.1k 24v 5v fault output input 0v gnd q1 irfz34 24v 2a solenoid 1910 f03 c1 100f 50v c t 1f 1 r s 0.02 (ptc) + figure 2. isolating the input figure 3. drain-sense con? guration
lt1910 8 1910fa to the supply at the same point as the positive end of the sense resistor. the drain-sense threshold voltage has a positive tempera- ture coef? cient, allowing ptc sense resistors to be used (see printed circuit board shunts). the selection of r s should be based on the minimum threshold voltage: r s = 50mv/i set thus the 0.02 drain-sense resistor in figure 3 will yield a minimum trip current of 2.5a. this simple con? guration is appropriate for resistive or inductive loads that do not generate large current transients at turn-on. automatic restart period the timing capacitor, c t , shown in figure 3 determines the length of time the power mosfet is held off follow- ing a current limit trip. curves are given in the typical performance characteristics to show the restart period for various values of c t . for example, c t = 0.33f yields a 50ms restart period. defeating automatic restart some applications are required to remain off after a fault occurs. when the lt1910 is being driven from cmos logic, this can be easily implemented by connecting resistor r2 between the in and timer pins as shown in figure 4. r2 supplies the sustaining current for an internal scr which latches the timer pin low under a fault condition. the fault pin is set active low when the timer pin falls below 3.3v. this keeps the mosfet gate from turning on and the applications information fault pin from resetting high until the in pin has been recycled. c t is used to prevent the fault pin from glitch- ing whenever the in pin recycles to turn on the mosfet unsuccessfully under an existing fault condition. inductive vs capacitive loads turning on an inductive load produces a relatively benign ramp in mosfet current. however, when an inductive load is turned off, the current stored in the inductor needs somewhere to decay. a clamp diode connected directly across each inductive load normally serves this purpose. if a diode is not employed, the lt1910 clamps the mosfet gate 0.7v below ground. this causes the mosfet to resume conduction during the current decay with (v + + v gs + 0.7v) across it, resulting in high dissipation peaks. capacitive loads exhibit the opposite behavior. any load that includes a decoupling capacitor will generate a current equal to c load ? (?v/?t) during capacitor in-rush. with large electrolytic capacitors, the resulting current spike can play havoc with the power supply and false trip the current-sense comparator. turn-on ?v/?t is controlled by the addition of the simple network shown in figure 5. this network takes advantage of the fact that the mosfet acts as a source follower during turn-on. thus the ?v/?t on the source can be controlled by controlling the ?v/?t on the gate. in timer fault 5v fault output r1 5.1k on = 5v off = 0v lt1910 gnd 1 1910 f04 4 r2 2k c t 1f 2 3 5v cmos logic v + sense 8 6 lt1910 1 gnd q1 irfz34 15v 1n4744 c load c2 50f 50v 1910 f05 r s 0.01 + + c d r d (10k) 1n4148 24v current limit delay network c1 1n4148 r1 100k r2 100k ?v/?t control network gate 5 figure 4. latch-off con? guration (autorestart defeated) figure 5. control and current limit delay
lt1910 9 1910fa applications information the turn-on current spike into c load is estimated by: ic vv rc peak load gth = ? ? ? 11 where v th is the mosfet gate threshold voltage. v g is obtained by plotting the equation: i v r gate gate = 1 on the graph of gate drive current (i gate ) vs gate voltage (v gate ) as shown in figure 6. the value of v gate at the intersection of the curves for a given supply is v g . for example, if v + = 24v and r1 = 100k, then v g = 18.3v. for v th = 2v, c1 = 0.1f and c load = 1000f, the estimated i peak = 1.6a. the diode and the second resistor in the network ensure fast current limit turn-off. when turning off a capacitive load, the source of the mosfet can hang up if the load resistance does not discharge c load as fast as the gate is being pulled down. if this is the case, a 15v zener may be added from gate to source to prevent v gs(max) from being exceeded. r d and c d delay the overcurrent trip for drain currents up to approximately 10 ? i set , above which the diode conducts and provides immediate turn-off (see figure 7). to ensure proper operation of the timer, c d must be c t . gate voltage (v) 0 gate drive current (a) 300 400 500 30 50 1910 f06 200 100 0 10 20 40 600 700 800 60 v + = 48v i gate = v gate /10 5 v + = 24v v + = 12v v + = 8v figure 6. gate drive current vs gate voltage adding current limit delay when capacitive loads are being switched or in very noisy environments, it is desirable to add delay in the drain current-sense path to prevent false tripping (inductive loads normally do not need delay). this is accomplished by the current limit delay network shown in figure 5. mosfet drain current (1 = set current) 1 0.01 trip delay time (1 = r d c d ) 0.1 1 10 10 100 1910 f07 figure 7. current limit delay time printed circuit board shunts the sheet resistance of 1oz copper clad is approximately 5 ? 10 C4 /square with a temperature coef? cient of 0.39%/c. since the lt1910 drain-sense threshold has a similar temperature coef? cient (0.33%/c), this offers the possibility of nearly zero tc current sensing using the free drain-sense resistor made out of pc trace material. a conservative approach is to use 0.02" of width for each 1a of current for 1oz copper. combining the lt1910 drain sense threshold with the 1oz copper resistance results in a simple expression for width and length: width (1oz cu) = 0.02" ? i set length (1oz cu) = 2" the width for 2oz copper would be halved while the length would remain the same. bends may be incorporated into the resistor to reduce space; each bend is equivalent to approximately 0.6 ? the width of a straight length. kelvin connection should be employed by running a separate trace from the ends of the resistor back to the lt1910s v + and sense pins. see application note 53 for further information on printed circuit board shunts.
lt1910 10 1910fa applications information low voltage/wide supply range operation when the supply is less than 12v, the lt1910s charge pump does not produce suf? cient gate voltage to fully enhance the standard n-channel mosfet. for these ap- plications, a logic-level mosfet can be used to extend the operating supply down to 8v. if the mosfet has a maximum v gs rating of 15v or greater, then the lt1910 can also operate up to a supply voltage of 60v (absolute maximum rating of the v + pin). protecting against supply transients the lt1910 is 100% tested and guaranteed to be safe from damage with 60v applied between the v + and gnd pins. however, when this voltage is exceeded, even for a few microseconds, the result can be catastrophic. for this reason it is imperative that the lt1910 is not exposed to supply transients above 60v. a transient suppressor, such as diodes inc.s smaj48a, should be added between the v + and gnd pins for such applications. for proper current sense operation, the v + pin is required to be connected to the positive side of the drain-sense resistor (see drain-sense con? guration). therefore, the supply should be adequately decoupled at the node where the v + pin and drain sense resistor meet. several hundred microfarads may be required when operating with a high current switch. when the operating voltage approaches the 60v absolute maximum rating of the lt1910, local supply decoupling between the v + and gnd pins is highly recommended. an rc snubber with a transient suppressor are an absolute necessity. note however that resistance should not be added in series with the v + pin because it will cause an error in the current-sense threshold. low side driving although the lt1910 is primarily targeted at high side (grounded load) switch applications, it can also be used for low side (supply connected load) switch applications. figures 8a and 8b illustrate the lt1910 driving low side power mosfets. because the lt1910 charge pump tries to pump the gate of the n-channel mosfet above the supply, a clamp zener is required to prevent the v gs (ab- solute maximum) of the mosfet from being exceeded. fault in v + sense 3 4 8 6 lt1910 r1 5.1k 12v to 48v 5v fault output input 0v gnd q1 irfz44 15v 1n4744 1910 f08a c1 100f 100v c t 1f r s 0.01 (ptc) 4a load + gate timer 5 1 2 fault in timer v + sense gate 3 4 2 8 6 5 lt1910 r1 5.1k 5v fault output input gnd q1 irf630 15v 1n4744 1910 f08b c1 10f 50v c t 1f 1 r s 0.02 hv load 51 2n2222 8v to 24v hv C + + lt1006 51 figure 8a. low side driver with load current sensing figure 8b. low side driver for source current sensing
lt1910 11 1910fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description applications information the lt1910 gate drive is current limited for this purpose so that no resistance is needed between the gate pin and zener. current sensing for protecting low side drivers can be done in several ways. in the figure 8a circuit, the supply voltage for the load is assumed to be within the supply operating range of the lt1910. this allows the load to be returned to supply through current-sense resistor, r s , providing normal operation of the lt1910 protection circuitry. if the load cannot be returned to supply through r s , or the load supply voltage is higher than the lt1910 supply, the current sense must be moved to the source of the low side mosfet. figure 8b shows an approach to source sensing. an operational ampli? er (must common mode to ground) is used to level shift the voltage across r s up to the drain- sense pin. this approach allows the use of a small sense resistor which could be made from pc trace material. the lt1910 restart timer functions the same as in the high side switch application. s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .016 C .050 (0.406 C 1.270) .010 C .020 (0.254 C 0.508) s 45 o 0 o C 8 o typ .008 C .010 (0.203 C 0.254) so8 0303 .053 C .069 (1.346 C 1.752) .014 C .019 (0.355 C 0.483) typ .004 C .010 (0.101 C 0.254) .050 (1.270) bsc 1 2 3 4 .150 C .157 (3.810 C 3.988) note 3 8 7 6 5 .189 C .197 (4.801 C 5.004) note 3 .228 C .244 (5.791 C 6.197) .245 min .160 p .005 recommended solder pad layout .045 p .005 .050 bsc .030 p .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
lt1910 12 1910fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0409 rev a ? printed in usa related parts typical application protected 1a automotive solenoid driver with overvoltage shutdown fault in timer v + sense gate 3 4 2 8 6 5 lt1910 r1 5.1k 5v fault output input power ground 8v to 24v operating 32v to 60v shutdown gnd q1 mtd3055el 24v 1a solenoid 1910 ta03 c1 10f 100v c t 1f r3 5.1k 1n4148 2n3904 1 r s 0.03 (ptc) + r2 10k 30v 1n6011b part number description comments lt c ? 1153 autoreset electronic circuit breaker programmable trip current, fault status output ltc1155 dual high side micropower mosfet driver operates from 4.5v to 18v, 85a on current, short-circuit protection lt1161 quad protected high side mosfet driver 8v to 48v supply range, individual short-circuit protection ltc1163 triple 1.8v to 6v high side mosfet driver 0.01a standby current, triple driver in so-8 package ltc1255 dual 24v high side mosfet driver operates from 9v to 24v, short-circuit protection ltc1477 protected monolithic high side switch low r ds(on) 0.07 switch, 2a short-circuit protected ltc1623 smbus dual high side switch controller 2-wire smbus serial interface, built-in gate charge pumps ltc1693 family high speed single/dual n-channel/p-channel mosfet drivers 1.5a peak output current, 4.5v v cc 13.2v, so-8 package ltc1710 smbus dual monolithic high side switch two low r ds(on) 0.4/300ma switches in 8-lead msop package ltc4412 low loss powerpath? controller implements ideal diode function, thinsot? package powerpath and thinsot are trademarks of linear technology corporation.

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